Parent application Ser. No. 715,691, now U.S. Pat. No. 4,086,862, discloses a sewing-machine stitch-pattern control circuit, in which any selected one of a plurality of patterns can be sewn. The stitch-control data for the plurality of patterns is stored in a read-only memory (ROM). The sewing-machine-synchronized read-out of the ROM is performed entirely without the use of addressing counters, and indeed with an addressing sequence which is derived from the signals produced at the outputs of the memory and which may have a very flexible character. In particular, each addressable storage unit within the ROM stores, not merely the stitch-control signals for one stitch of one of the patterns, but also information concerning the address of the storage location containing the stitch-control signals for the next stitch of that pattern.
When the operator selects one of the patterns, his selection determines the address of the first stitch-data-containing storage location to be read out in the ROM. The signals produced at the ROM outputs in response to read-out of the first-stitch data are used to address the next storage location to be read out from the ROM. Such next-address signals are produced at separate next-address signal outputs of the ROM, or else are derived from the stitch-control signals at the output of the ROM, or are derived from ROM output signals in more complicated ways disclosed in that patent. The read-out of the addressable ROM is accordingly not effected under the control of an addressing counter. Typical prior-art addressing counters establish a fixed sequence for the successive address signals to be read out from the ROM. In contrast, with the stitch-pattern control circuit disclosed in the above-identified patent, reference to an outside counter which dictates the read-out sequence is absent. Instead, the data content of each storage location read out itself determines what the next storage location to be read out should be.
On a practical level, the elimination of the use of prior-art addressing counters greatly increases the freedom with which data pertaining to individual stitches of plural selectable patterns can be assigned to storage locations within the ROM. To explain this, the following, somewhat oversimplified and exaggerated illustration is given. With a stitch-data ROM addressed by a prior-art addressing counter, the operator when he selects a pattern in effect selects the first one or two highest-place digits of a storage-location address, e.g., 100, 200, 300 or 400, etc. Then, when machine-synchronized read-out of the stitch data pertaining to the selected pattern begins, the addressing counter commences to add to the selected initial address (100 or 200 or 300 etc.) lower-value numbers, e.g., in the sequence 1, 2, 3, 4, etc. As a result, the first stored pattern, if selected by the operator, is read out using a storage-location address sequence 100, 101, 102, 103, 104, etc. If the operator selects the second stored pattern, it is read out using a storage-location address sequence 200, 201, 202, 203, 204, etc.
Thus, when the operator selects which stitch-pattern is to be read out, in effect he picks out the first 100 storage locations, or the second 100 storage locations, or the third 100 storage locations, etc., and then the addressing counter performs the read-out of the successive storage locations within the selected 100 storage locations. Clearly, when assigning storage locations to the stitch data of one pattern to be stored, these must all go into one of the selectable groups of 100 storage locations. On a first level, this can be wasteful of storage locations, in the sense that it may be desirable to store a mixture of few-stitch stitch patterns and many-stitch stitch patterns, requiring that each operator-selectable group of storage locations be large in number (to be able to accommodate the many-stitch stitch patterns) whereas the few-stitch stitch patterns very incompletely fill the storage-location groups they occupy. The inventive elimination of the prior-art use of addressing counters to read out the stitch-data ROM avoids this problem.
However, on a deeper level, the characteristic next-address-signal technique of the present invention, avoiding as it does the use of addressing counters, creates greater system flexibility in general, and not merely with respect to storage of few-stitch and many-stitch stitch patterns. For example, when the operator makes a pattern selection, this serves, in a way similar to prior art, to establish the one or few highest-value digits of the first address signal to be applied to the ROM to read it out. However, the lower-value digits of the first address signal need not come from the operator-activated pattern selector nor from an addressing counter. Thereafter, i.e., for subsequent stitches, all lower-value digits of each subsequent signal, and/or perhaps one or more of the highest-value digits of the address signals, are derived from the output signals of the ROM.
In principle, all digits of all succeeding address signals could be derived from the output signals of the ROM. In this way, the stitch-data memory becomes a very independent unit whose read-out sequence is controlled, so the speak, from the inside out, the content of each addressed storage location itself determining what storage location should next be read out, with little or no reference to outside control for determining the address of the next location to be read out. Accordingly, if a system is designed for a particular stitch-pattern ROM containing a predetermined plurality of specific stored stitch patterns, replacement of that ROM with another containing other stored stitch patterns organized in a quite different way will not necessarily call for modification of any neighboring components of the stitch-pattern control circuit. For example, if the largest number of stitches in any stored pattern is sixteen, a typical prior-art addressing counter must be able to count to sixteen, to be able to read-out such a pattern. If then, the ROM is replaced by another whose largest stored stitch pattern includes a greater number of stitches, this would require replacement of the addressing counter with another having the requisite increased counting capacity.
In contrast, with the next-address-signal technique of the present invention, such a modification of components cooperating with the replaced ROM would not be necessary, because the new ROM itself controls its own read-out, so to speak from the inside out. This is an example of the type of greater system flexibility in question, and is disclosed in the patent identified above.
The present invention relates to further developments upon systems of that type. Firstly, the invention contemplates stitch-pattern control either under the control of such ROM or, alternatively, under the control of pattern data furnished from an external pattern reading device, e.g., a perforated-tape reading device. To this end, the present invention provides an intermediate second memory, connected between the outputs of the first memory and the inputs to the stitch-forming instrumentalities. When it is desired that one of the stitch patterns stored in the first memory be sewn, the selected pattern is read out from the first memory at high speed, not synchronized to sewing-machine operation, and written into the intermediate second memory. Thereafter, the pattern information thusly transferred to the second memory is read out in synchronism with sewing-machine operation and applied to the stitch-forming instrumentalities. This creates the possibility to write into the second memory information derived, not from the first memory, but derived instead from the external pattern reader, e.g., a perforated-tape reader or the like.
When two memories are thusly employed, one or both can be addressed for read-out in accordance with the inventive next-address-signal technique without reliance on read-out addressing counters. Alternatively, only the first memory might be so addressed, and the second memory be addressed for write-in and/or read-out in a different way.
In one embodiment of the invention, the second memory is a RAM having stitch-control signal inputs and outputs, and also having next-address-signal inputs and outputs in addition to its address-signal inputs. The read-out of the first memory is effected using the next-address-signal technique in question. The stitch-control information written into the second memory is written in along with a series of next-address signals. This occurs at high speed, not in synchronism with sewing-machine operation. Thereafter, the machine-synchronized read-out of the second memory is likewise effected using the next-address-signal technique in question, the signals produced at the next-address signal outputs of the second memory being fed back to the address signal inputs thereof.
In another embodiment, the first memory is a static random-access read-only memory, but the second memory is a sequential-access dynamic memory, e.g., a circulating or reentrant shift register memory. Again, the read-out of the first memory and the transfer of its information to the second memory is effected at high speed, not in synchronism with machine operation. Thereafter, the read-out of the sequential-access dynamic memory is performed in synchronism with sewing-machine operation, but does not involve the use of an addressing code, or the like, the read-out instead being performed by a train of machine-synchronized read-out pulses indistinguishable from one another.
The novel features which are considered as characteristic for the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.